The present disclosure relates to low power circuit design, and to designing a low power circuit using clock gating, in particular.
One of the most challenging tasks in chip design is to reduce power consumption in electronic chip designs. Among the many techniques for power reduction, clock gating is one of the most known and widely used. Clock gating reduces the power consumption by partially disabling portions of the circuitry not required for the operation of the circuitry at a given cycle. A flip-flop of a circuitry consumes power when it receives a clock signal, indicating a new cycle, and re-computes its value. Using clock gating technique, the clock signal to the flip-flop is blocked when the recomputed value of the flip-flop is not required in order for the circuitry to behave according to its design. A logic blocking the clock signal is also referred to as clock gating function.
The value of the flip-flop may not be required if its value is not recomputed, and the circuitry still behaves correctly. For example, if the recomputed value is the same as the current value—recomputation may not be required. An additional exemplary scenario in which a recomputed value is not required may be a case in which the recomputed value is later used in a logical operator whose value does not depend on the recomputed value. Such is the case if the recomputed value is later on ANDed with a ZERO value—the truth value of the AND component is zero, independent of the recomputed value.
It will be noted that in the present application, flip-flops refer to any form of state storage devices. Unless explicitly stated otherwise, flip-flops refer also to latches.